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Altera Unveils Innovations at 20 nm

Altera’s Next-Generation Devices Extend the Promise of Silicon Convergence

San Jose, Calif., September 5, 2012 /PRNewswire/ — Altera Corporation (NASDAQ: ALTR) today unveiled several key innovations planned for its next generation of 20-nm products. Extending the promise of silicon convergence, Altera is offering customers the ultimate system-integration platform, combining the hardware programmability of FPGAs with the software flexibility of digital signal processors and microprocessors along with the efficiencies of application-specific hard intellectual property (IP). The architectural, software and process innovations Altera is making at 20 nm enable the development of an enhanced mixed-system fabric that delivers new levels of performance, bandwidth, integration and power efficiency.

Altera’s 20-nm mixed-system fabric includes the integration of 40-Gbps transceiver technology, a next-generation variable-precision digital signal processing (DSP) block architecture that delivers over 5 TFLOPs of IEEE 754 floating-point performance, and heterogeneous 3D ICs that integrate FPGAs with a user-customizable HardCopy® ASIC or a variety of other technologies, including memory, third-party ASICs and optical interfaces through an innovative high-speed interface. Altera is the only company in the industry able to integrate FPGAs with ASICs into a single device.

The 20-nm mixed-system fabric also offers continued innovations in power management, including adaptive voltage scaling, Programmable Power Technology, and optimized process technology, which enable Altera to reduce device power consumption up to 60 percent compared to its previous generation of devices.

Development of heterogeneous 20-nm systems are supported through a full-featured, high-level design environment that includes system-level design tools (Qsys), C-based design tools (OpenCL™) and DSP development software (DSP Builder). Altera continues its focus on designer productivity by scaling its development tools to deliver the industry’s fastest compile times at 20 nm.

“Designers of next-generation communications, networking, broadcast and computing applications are faced with the ever-increasing need for expanded bandwidth, higher performance and lower power,” said Bradley Howe, senior vice president of research and development at Altera. “Our innovations at 20 nm allow us to deliver a highly efficient, highly flexible mixed-system fabric that features optimal levels of dedicated circuitry with the latest 20‑nm FPGA process technology. The result is a device that delivers the industry’s highest levels of IC integration, performance and bandwidth at the lowest power.”

Altera’s next-generation devices leverage TSMC’s 20-nm process technology and include the industry’s highest levels of system integration, including a hard ARM® processor subsystem. 20-nm system-on-chip (SoC) FPGAs provide customers a software migration path from 28 nm to 20 nm while delivering a 50 percent processor subsystem performance increase.

Coming innovations include the following:
Highest Serial Bandwidth: 40-Gbps Chip-to-Chip and 28-Gbps Backplane Transceivers

Innovations made to Altera’s transceiver technology at 20 nm deliver the industry’s highest serial bandwidth, enabling the migration to 100G backplane and 400G systems. The 20‑nm devices will include both 28-Gbps transceivers to drive CEI-25G-LR, Ethernet 4×25G backplanes and 40-Gbps transceivers designed to interface with chip-to-chip or chip-to-optical modules. The transceiver technology innovations Altera is making at 20 nm provide the foundation for developing CEI-56G-compliant transceivers that offer the connectivity to drive the next generation of 400G optical networks, 400G line cards and beyond.

 Heterogeneous 3D ICs Featuring a High-Speed Chip-to-Chip Interface
At 20-nm, Altera will introduce an innovative high-speed chip-to-chip interface that integrates multiple dies together in a 3D package. This innovative interface enables Altera to deliver customer-specific heterogeneous 3D systems that mix FPGAs with a user-customizable HardCopy ASIC, or a variety of other technologies, including memory, third-party ASICs and optical interfaces. Integrating FPGAs with HardCopy ASICs or third-party ASICs makes it possible for Altera to deliver single-device solutions that offer 10X higher system integration versus any 28-nm product. Altera’s heterogeneous 3D ICs will be manufactured using TSMC’s chip-on-wafer-on-substrate (CoWoS) process. The devices will enable developers to dramatically increase system integration, system performance and product differentiation while reducing system power, board space and costs.

Industry’s Highest DSP Performance with Highest TFLOPs/Watt
Altera is resetting industry benchmarks in TFLOPs/watt with 20-nm devices. Enhancements made to its next-generation variable-precision DSP block deliver over 5 TFLOPs of IEEE 754 floating-point performance. At these levels, Altera’s 20-nm devices deliver over 5X higher TFLOPs per watt versus competitive FPGAs. Combining the productivity benefits of an OpenCL C-based design flow, an ARM hard processor subsystem and the highest TFLOPs/watt silicon efficiency, Altera’s 20-nm devices provide the ultimate heterogeneous computing platform.

Altera is currently engaging with customers on its 20-nm products and mutually discussing product roadmaps. More information about Altera’s 20-nm products can be found at www.altera.com/20nm. A white paper that discusses Altera’s 20-nm innovations can be found at www.altera.com/20nmWP. To get an update on Altera’s 20-nm products or to discuss advantages to leveraging Altera’s solutions in next-generation systems, readers should contact a local Altera sales representative.

About Altera
Altera® programmable solutions enable system and semiconductor companies to rapidly and cost effectively innovate, differentiate and win in their markets. Find out more about Altera’s FPGA, SoC FPGA, CPLD and ASIC devices at www.altera.com. Follow Altera via Facebook, RSS and Twitter.

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